The present invention relates, generally, to semiconductor devices and. more particularly, to semiconductor devices having metallized interconnect structures and to methods for their fabrication.
Advanced integrated circuits typically employ numerous metal interconnect layers overlying integrated circuit components formed on a semiconductor substrate. The metal interconnect layers are vertically arranged over the device components and are separated from one another by inter-level-dielectric (ILD) layers. The metal interconnect layers are electrically connected through structures, known as vias and contacts, formed in the ILD layers. A via, for example, is an opening formed in an ILD layer positioned between two vertically separated metal interconnect layers. Correspondingly, a contact is an opening in an insulating layer that overlies the device component. An electrical connection is made to the substrate or to a device component through the contact opening. Advanced integrated circuits employ numerous contacts and vias to electrically connect millions of transistors and other components used in an integrated circuit device.
As the feature sizes of integrated circuit components is reduced to smaller and smaller dimensions, the alignment tolerances for fabrication of the integrated circuit must also be reduced. Typically, as the feature size of an integrated circuit is reduced all critical dimensions are correspondingly scaled to reflect the smaller feature size. This means that, for example, the lateral width of conductors, such as metal interconnects, gate electrodes, and the like, is reduced by a scaling factor. In addition to line widths, the size of via openings and contact openings are also scaled to smaller dimensions.
If the contact and via openings could be reduced in size by the same factor as the line width of other device components, the alignment tolerance to which the integrated circuit is fabricated would not change. The fabrication of a low resistance metal interconnect structure, however, requires that a certain amount of contact area exist at the interface between a metallized interconnect, such as via plug, to maintain a sufficiently small contact resistance. Also, the overall integrated circuit design parameters, require that the device function at specified signal frequencies. The maintenance of the signal frequency, in turn, requires that the contact resistance not be excessively large.
To satisfy the low contact resistance requirements as the feature sizes are reduced and the design tolerances are decreased, the contact and via dimension are not reduced to the same extent as the characteristic line width of the underlying device components. This results in a design criteria known as xe2x80x9czero overlap.xe2x80x9d Under a zero overlap design tolerance, the contact or via opening is aligned very close to the edge of the underlying device component.
A typical arrangement is shown in the cross-sectional view of FIG. 1A, where a semiconductor substrate 10 supports a device layer 12. A conductor 14 overlies a portion of the device layer and an ILD layer 16 overlies conductor 14. A via opening 18 in ILD layer 16 exposes a contact portion 20 of conductor 14. Under stringent alignment tolerances, via opening 18 is positioned in close proximity to a wall surface 22 of conductor 14. As illustrated in the top view shown of FIG. 1B, opening 18 is positioned in close proximity to wall surface 22 and to a lateral wall surface 24.
Opening 18 is positioned a distance D1 from wall surface 22 and a distance D2 from wall surface 24. Under the design rules illustrated in FIG. 1B, opening 18 will always be positioned at a specified distance. D1 and D2, from the wall surfaces of conductor 14. The design rules specifying D1 and D2 are developed for a specific line width W. As the line width W is reduced, in order for via opening 18 to remain at a constant size, D1 and D2 must also be reduced. As the dimensions D1 and D2 are reduced, however, the possibility for misalignment increases. FIG. 1C illustrates a misaligned condition in which via opening 18 has been misaligned to conductor 14. A portion of via opening 18 exposes a wall surface 22 of conductor 14.
The misalignment of via opening 18 to conductor 14 adversely affects devire performance by undesirably increasing contact resistance. The increased contact resistance arises through both a reduced contact area and through damage to conductor 14 during fabrication of the via opening. Accordingly, a need existed for a metallized interconnect structure and method of fabrication that allows for contact misalignment, while maintaining good contact integrity and low contact resistance.
The present invention provides a metallized interconnect structure and method of fabrication that fully compensates for misalignment of via and contact openings in integrated circuits and other semiconductor devices fabricated to zero-overlap design tolerances. In accordance with one aspect of the invention, a semiconductor device includes a conductor having an upper contact surface and an edge surface depending from the upper contact surface. An insulating layer overlies the conductor and an opening in the insulating layer exposes at least a portion of the upper contact surface. The opening also exposes at least a portion of the edge surface. A liner material covers at least the edge surface of the conductor that is exposed by the opening.
In another aspect of the invention, a process is provided for fabricating a metallized interconnect structure that includes providing a first conductor and an insulating layer overlying the first conductor. The first conductor has an upper contact surface and an edge surface depending from the upper contact surface. An opening is formed in the insulating layer that exposes at least a portion of the upper contact surface and at least a portion of the edge surface. A liner is formed to overlie at least the portion of the edge surface that is exposed by the opening. The opening is then filled with an electrically conductive material.